Mistral - a Cyclone V FPGA bitstream library

• The Cyclone V FPGA
  • The FPGAs
  • Bitstream stucture
  • Logic blocks
  • Routing network
  • Programmable inverters
• CycloneV internals description
  • Routing network
  • Inner logic blocks
    • LAB
    • MLAB
    • DSP
    • M10K
  • Peripheral logic blocks
    • GPIO
    • DQS16
    • FPLL
    • CBUF
    • CMUXCR
    • CMUXHG
    • CMUXVG
    • CMUXHR
    • CMUXVR
    • CMUXP
    • CTRL
    • HSSI
    • HIP
    • DLL
    • SERPAR
    • LVL
    • TERM
    • PMA3
    • HMC
    • HPS
      • HPS_BOOT
      • HPS_CLOCKS
      • HPS_CLOCKS_RESETS
      • HPS_CROSS_TRIGGER
      • HPS_DBG_APB
      • HPS_DMA
      • HPS_FPGA2HPS
      • HPS_FPGA2SDRAM
      • HPS_HPS2FPGA
      • HPS_HPS2FPGA_LIGHT_WEIGHT
      • HPS_INTERRUPTS
      • HPS_JTAG
      • HPS_LOAN_IO
      • HPS_MPU_EVENT_STANDBY
      • HPS_MPU_GENERAL_PURPOSE
      • HPS_PERIPHERAL_CAN
      • HPS_PERIPHERAL_EMAC
      • HPS_PERIPHERAL_I2C
      • HPS_PERIPHERAL_NAND
      • HPS_PERIPHERAL_QSPI
      • HPS_PERIPHERAL_SDMMC
      • HPS_PERIPHERAL_SPI_MASTER
      • HPS_PERIPHERAL_SPI_SLAVE
      • HPS_PERIPHERAL_UART
      • HPS_PERIPHERAL_USB
      • HPS_STM_EVENT
      • HPS_TEST
      • HPS_TPIU_TRACE
  • Options
• CycloneV library usage
  • Library structure
  • Packages
  • Model information
  • pos, rnode and pnode
  • Routing network management
  • Logic block management
  • Inverters management
  • Pin/package management
  • Options
  • Bitstream management
  • HMC bypass
• The mistral-cv command-line program
  • models
  • routes
  • routes2
  • cycle
  • bels
  • decomp
  • comp
  • diff
• Mistral CycloneV library internals
  • Structure
  • Routing data
  • Block muxes
  • Logic blocks
  • Inverters
  • Forced-1 bits
  • Packages
  • Models